supertex inc. supertex inc. www.supertex.com hv57009 doc.# dsfp-hv57009 a061913 features ? hvcmos ? technology ? 5.0v cmos logic ? output voltage up to -85v ? output current source control ? 16mhz equivalent data rate ? latched data outputs ? forward and reverse shifting options (dir pin) ? diode to vdd allows eficient power recovery functional block diagram 64-channel serial to parallel converter with p-channel open drain controllable output current general description the hv57009 is a low-voltage serial to high-voltage parallel converter with p-channel open drain outputs. this device has been designed for use as a driver for plasma panels. the device has two parallel 32-bit shift registers, permitting data rates twice the speed of one (they are clocked together). there are also 64 latches and control logic to perform the blanking of the outputs. hv out 1 is connected to the irst stage of the irst shift register through the blanking logic. data is shifted through the shift registers on the logic low to high transition of the clock. the dir pin causes ccw shifting when connected to vss, and cw shifting when connected to vdd. a data output buffer is provided for cascading devices. this output relects the current status of the last bit of the shift register (hv out 64). operation of the shift register is not affected by the le (latch enable), or the bl (blanking) inputs. transfer of data from the shift registers to latches occurs when the le input is high. the data in the latches is stored when le is low. the hv570 has 64 channels of output constant current sourcing capability. they are adjustable from 0.1 to 2.0ma through one external resistor or a current source. hv out 1 hv out 2 hv out 3 ?? ? hv out 32 hv out 33 hv out 34 hv out 35 ?? ? hv out 64 latch latch latch latch vdd vss bl le clk dir vbp +in -in d i/o 2b note: each sr (shift register) provides 32 outputs. sr1 supplies outputs 1 to 32 and sr2 supplies outputs 33 to 64. programmable current d i/o 1b sr2 i/o d i/o 2a d i/o 1a i/o sr1 downloaded from: http:///
2 supertex inc. www.supertex.com doc.# dsfp-hv57009 a061913 hv57009 absolute maximum ratings parameter value supply voltage, v dd 1 -0.5v to +7.5v output voltage , v nn 1 v dd + 0.5v to -95v logic input levels 1 -0.3v to v dd +0.3v ground current 2 1.5a continuous total power dissipation 3 1200mw operating temperature range -40c to +85c storage temperature range -65c to +150c recommended operating conditions sym parameter min max units v dd logic supply voltage 4.5 5.5 v hv out hv output off voltage -85 v dd v v ih high-level input voltage v dd -1.2v v dd v v il low-level input voltage 0 1.2 v f clk clock frequency per register dc 8.0 mhz 4.5 t a operating free-air temperature -40 +85 c notes: power-up sequence should be the following: 1. connect ground 2. apply v dd 3. set all inputs to a known statepower-down sequence should be the reverse of the above. pin coniguration 1 80 80-lead pqfp hv57009pg llllllllll yyww cccccccc aaa l = lot number yy = year sealed ww = week sealed c = country of origin a = assembler id = ?green? packagin g product marking 80-lead pqfp absolute maximum ratings are those values beyond which damage to the device may occur. functional operation under these conditions is not implied. continuous operation of the device at the absolute rating level may affect device reliability. notes: 1. all voltages are referenced to v ss . 2. duty cycle is limited by the total power dissipated in the package. 3. for operation above 25c ambient derate linearly to maximum operating temperature at 20mw/c. package may or may not include the following marks: si or ordering information part number package option packing HV57009PG-G 80-lead pqfp 66/tray typical thermal resistance package ja 80-lead pqfp 37 o c/w -g denotes a lead (pb)-free / rohs compliant package downloaded from: http:///
3 supertex inc. www.supertex.com doc.# dsfp-hv57009 a061913 hv57009 dc electrical characteristics (all voltages are referenced to v ss , v ss = 0, t a = 25 o c) sym parameter min max units conditions i dd v dd supply current - 15 ma v dd = v dd max, f clk = 8.0mhz i nn high voltage supply current - -10 a outputs off, hv out = -85v (total of all outputs) i ddq quiescent v dd supply current - 100 a all inputs = v dd , except +in = v ss = gnd v oh high level output data out v dd -0.5v - v i o = -100a hv out +1.0 v dd v i o = -2.0ma v ol low level output data out - +0.5 v i o = 100a i ih high-level logic input current - 1.0 a v ih = v dd i il low-level logic input current - -1.0 a v il = 0v i cs high output source current - -2.0 ma v ref = 2.0v, r ext = 1.0k, see figures 1a and 1b -0.1 - v ref = 0.1v, r ext = 1.0k, see figures 1a and 1b i cs hv output source current for i ref = 2.0ma - 10 % v ref = 2.0v, r ext = 1.0k note: current going out of the chip is considered negative . ac electrical characteristics (logic signal inputs and data inputs have t r , t f 5ns [10% and 90% points] for measurements) sym parameter min max units conditions f clk clock frequency dc 8.0 mhz per register 4.5 when cascading devices t wl , t wh clock width high or low 62 - ns --- t su data set-up time before clock rises 20 - ns --- t h data hold time after clock rises 15 - ns --- t on , t off time from latch enable to hv out - 500 ns c l = 15pf t dhl delay time clock to data high to low - 150 ns c l = 15pf t dlh delay time clock to data low to high - 150 ns c l = 15pf t dle delay time clock to le low to high 45 - ns --- t wle le pulse width 25 - ns --- t sle le set-up time before clock rises 0 - ns --- t r , t f max. allowable clock rise and fall time(10% and 90% points) - 100 ns --- downloaded from: http:///
4 supertex inc. www.supertex.com doc.# dsfp-hv57009 a061913 hv57009 input and output equivalent circuits data input vdd logic inputs dataoutput logic data output to internal circuits vss analog input i cs hvout high voltage output vdd vss vdd vss vdd pcntrl data input shift register operation 25 26 36 37 hv out 33 ?? ? ? ? hv out 63 hv out 64 pin dir = vdd dir = vss sr1 cw dir = vdd; cw (hv out 1hv out 64) dir = vss; ccw (hv out 64hv out 1) d i/o 1a d i/o 2a d i/o 2b d i/o 1b d i/o 2a d i/o 1a d i/o 1b d i/o 2b hv out 32 ?? ? ? ? hv out 2 hv out 1 cw sr1 downloaded from: http:///
5 supertex inc. www.supertex.com doc.# dsfp-hv57009 a061913 hv57009 switching waveforms le hv out w/ data input low previous i o = i ref previous i o = 0 i o = 0 i o = i ref data valid 50% 50% dat a inpu t cl k dat a ou t 50% 50% 50% t su t h t wl t wh 50% t dlh t dlh 50% t wle t dle t sle 50% 50% t on 10% 90% 90% 10% t off v dd v ss v dd hv out (off) 10% 90% 90% 10% 50% t f t r hv out w/ data input high v dd v ss v dd v ss v dd v ss v dd v ss v dd hv out (off) function table function inputs outputs data in clk le bl dir shift reg hv outputs data out all o/p high x x x l x * on * data falls through (latches transparent) l _ _ h h x l.....l on l h _ _ h h x h.....h off h data stored in latches x x l h x * inversion of stored data * i/o relation d i/o 1-2a _ _ h h h q n q n+1 new on or off d i/o 1-2b d i/o 1-2a _ _ l h h q n q n+1 previous on or off d i/o 1-2b d i/o 1-2b _ _ l h l q n q n-1 previous on or off d i/o 1-2a d i/o 1-2b _ _ h h l q n q n-1 new on or off d i/o 1-2a note: * = dependent on previous stages state. see figure 7 for din and dout pin designation for cw and ccw shift. h = v dd (logic)/v nn (hv outputs) l = v ss downloaded from: http:///
6 supertex inc. www.supertex.com doc.# dsfp-hv57009 a061913 hv57009 typical current programing circuits +in -in r d *10k hv57009 logic to other outputs - + vref i out hvout vdd 0.1f vbp i ref r et +in -in d *0pf hv57009 logic to other outputs -+ vss figure 1b: positive control figure 1a: negative control vref i out hvout vdd vbp i ref r et vss 0.1f r d *10k d *0pf *required if r ext > 10k? or r ext is replaced by a constant current source. since: i out = i ref = v ref / r ext therefore: if i out = 2.0ma and v ref = -5.0v r ext = 2.5k?. if i out = 1.0ma and r ext = 1.0k? v ref = -1.0v. if r ext >10k?, add series network r d and c d to ground for stability as shown. this control method behaves linearly as long as the opera - tional ampliier is not saturated. however, it requires a nega - tive power source and needs to provide a current i ref = i out for each hv570 chip being controlled.if hv out +1.0v, the hv out cascade may no longer oper - ate as a perfect current source, and the output current will diminish. this effect depends on the magnitude of the output current. given i out and v ref , the r ext can be calculated by using: r ext = v ref / i ref = v ref / i out the intersection of a set of i out and v ref values can be lo - cated in the graph shown below. the value picked for r ext must always be in the shaded area for linear operation. this control method has the advantage that v ref is positive, and draws only leakage current. if r ext > 10k?, add series net - work r d and c d to ground for stability as shown. note: lower reference current i ref , results in higher distortion, ?i cs , on the output. hv57009 i out vs. v ref 4 3 2 1 0 0 1 2 3 4 5 v ref (v) i out (ma) 0.1k 0.2k 0.5k 1.0k 2.0k 3.0k 5.0k downloaded from: http:///
7 supertex inc. www.supertex.com doc.# dsfp-hv57009 a061913 hv57009 pin function pin # function 1 hv out 24 2 hv out 23 3 hv out 22 4 hv out 21 5 hv out 20 6 hv out 19 7 hv out 18 8 hv out 17 9 hv out 16 10 hv out 15 11 hv out 14 12 hv out 13 13 hv out 12 14 hv out 11 15 hv out 10 16 hv out 9 17 hv out 8 18 hv out 7 19 hv out 6 20 hv out 5 pin # function 21 hv out 4 22 hv out 3 23 hv out 2 24 hv out 1 25 d i/o 1a 26 d i/o 2a 27 nc 28 nc 29 le 30 clk 31 bl 32 vss 33 dir 34 vdd 35 -in 36 d i/o 2b 37 d i/o 1b 38 nc 39 +in 40 vbp pin # function 41 hv out 64 42 hv out 63 43 hv out 62 44 hv out 61 45 hv out 60 46 hv out 59 47 hv out 58 48 hv out 57 49 hv out 56 50 hv out 55 51 hv out 54 52 hv out 53 53 hv out 52 54 hv out 51 55 hv out 50 56 hv out 49 57 hv out 48 58 hv out 47 59 hv out 46 60 hv out 45 pin # function 61 hv out 44 62 hv out 43 63 hv out 42 64 hv out 41 65 hv out 40 66 hv out 39 67 hv out 38 68 hv out 37 69 hv out 36 70 hv out 35 71 hv out 34 72 hv out 33 73 hv out 32 74 hv out 31 75 hv out 30 76 hv out 29 77 hv out 28 78 hv out 27 79 hv out 26 80 hv out 25 notes: 1. pin designation for dir = vdd. 2. a 0.1f capacitor is needed between vdd and vbp (pin 40) for better output current stability and to prevent transient cross-coupling between outputs. see figures 1a and 1b. downloaded from: http:///
supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives an adequate ?product liability indemnification insurance agreement.? supertex inc . does not assume responsibility for use of devices described, and limits its liabilit y to the replacement of the devices determined defective due to workmanship. no responsibility is assumed for possible omissions and inaccuracies. circuitry and specifications are subject to change without notice. for the latest product specifications refer to the supertex inc . (website: http//www .supertex.com) ?2013 supertex inc. all rights reserved. unauthorized use or reproduction is prohibited. supertex inc. 1235 bordeaux drive, sunnyvale, ca 94089 t el: 408-222-8888 www.supertex.co m 8 hv57009 (the package drawing(s) in this data sheet may not relect the most current speciications. for the latest package outline information go to http://www.supertex.com/packaging.html .) doc.# dsfp-hv57009 a061913 80-lead pqfp package outline (pg) 20.00x14.00mm body, 3.40mm height (max), 0.80mm pitch, 3.90mm footprint symbol a a1 a2 b d d1 e e1 e l l1 l2 1 dimen- sion (mm) min 2.80* 0.25 2.55 0.30 23.65* 19.80* 17.65* 13.80* 0.80 bsc 0.73 1.95 ref 0.25 bsc 0 o 5 o nom - - 2.80 - 23.90 20.00 17.90 14.00 0.88 3.5 o - max 3.40 0.50* 3.05 0.45 24.15* 20.20* 18.15* 14.20* 1.03 7 o 16 o jedec registration mo-112, variation cb-1, issue b, sept.1995. * this dimension is not speciied in the jedec drawing. drawings not to scale. supertex doc. #: dspd-80pqfppg, version c041309. 1 80 top vi ew vi ew b side view seating plane gauge plane l l1 l2 view b seating plane a2 a a1 d e e1 d1 b note 1 (index area d1/4 x e1/4) e 1 note: 1. a pin 1 identiier must be located in the index area indicated. the pin 1 identiier can be: a molded mark/identiier; an embedded metal marker; or a printed indicator. downloaded from: http:///
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